Integrated circuit devices with non-collapsed fins and methods of treating the fins to prevent fin collapse

ABSTRACT

An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/327,033 filed Feb. 21, 2019, which is a U.S. National PhaseApplication under 35 U.S.C. § 371 of International Application No.PCT/US2016/054641 filed Sep. 30, 2016. Each of these applications areincorporated herein by reference in their entirety.

BACKGROUND

A field-effect transistor (FET) is a semiconductor device that generallyincludes a gate, a source, and a drain. In operation, a FET uses anelectric field applied to the gate to control the electricalconductivity of a channel through which charge carriers (e.g., electronsor holes) flow from the source to the drain. A gate dielectric is usedto separate the gate from other regions of the FET, including the sourceand drain as well as the channel that connects source and drain when thetransistor is biased to an on or otherwise conductive state (as opposedto an off-state or non-conductive state). FETs can be implemented inboth planar and non-planar architectures. For instance, a finFET is anon-planar transistor built around a thin strip of semiconductormaterial (generally referred to as a fin). A finFET includes thestandard FET nodes, including a gate, a gate dielectric, a source, and adrain. The conductive channel of the device resides on the outerportions of the fin adjacent to the gate dielectric. Specifically,current runs along/within both sidewalls of the fin (sides perpendicularto the substrate surface) as well as along the top of the fin (sideparallel to the substrate surface). Because the conductive channel ofsuch configurations essentially resides along the three different outer,planar regions of the fin, such a finFET design is sometimes referred toas a tri-gate transistor. Another type of finFET is the so-calleddouble-gate finFET configuration, in which the conductive channelprincipally resides only along the two sidewalls of the fin (and notalong the top of the fin). Another non-planar transistor configurationis sometimes referred to as a nanowire configuration, which isconfigured similarly to a fin-based transistor, but instead of a finnedchannel region, one or more nanowires (or nanoribbons, depending onaspect ratio) are used and the gate material generally surrounds eachnanowire. Such nanowire configurations are sometimes calledgate-all-around FETs. For any such configurations, and as will beappreciated in light of this disclosure, fin collapse is an issue.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1E illustrate different integrated circuit structures inaccordance with various embodiments of the present disclosure, all withfins in a non-collapsed state.

FIG. 2 illustrates an integrated circuit structure with fins that havecollapsed.

FIG. 3A-3C are illustrations of surface tension, meniscus interaction,and hydrostatic pressure on the fins.

FIG. 3D illustrates the mathematical equation used to calculate findeflection based upon surface tension, meniscus interaction andhydrostatic pressure on the fins.

FIGS. 4A-8C are graphical illustrations depicting the conditions inwhich fin collapse occurs with a fin-based transistor device when thefins are not treated with the various treatments discussed herein.

FIG. 9A illustrates a SEM image of an integrated circuit structure withsome fin collapse.

FIG. 9B illustrates a SEM image of an integrated circuit structureaccording to one embodiment of the present disclosure where each of thefins is in a non-collapsed state.

FIG. 10 is a schematic illustration of a self-assembled monolayer usedin a method of forming an integrated circuit device in accordance withone embodiment of the present disclosure.

FIGS. 11A and 11B each illustrates a perspective view of an integratedcircuit device that is configured in accordance with one embodiment ofthe present disclosure.

FIGS. 12A-12C each illustrates a perspective view of an integratedcircuit device that is configured in accordance with other embodimentsof the present disclosure.

FIG. 13 illustrates a computing system implemented with one or moreintegrated circuit structures configured in accordance with anembodiment of the present disclosure.

As will be appreciated, the figures are not necessarily drawn to scaleor intended to limit the claimed scope to the specific configurationsshown. For instance, while some figures generally indicate straightlines, right angles, and smooth surfaces, an actual implementation of anintegrated circuit structure may have less than perfect straight lines,right angles, and some features may have surface topology or otherwisebe non-smooth, given real world limitations of the processing equipmentand techniques used. In short, the figures are provided merely to showexample structures.

DETAILED DESCRIPTION

The present disclosure is directed to integrated circuit devices andmethods for forming integrated circuit devices with fin-based transistorstructures, such as finFET and nanowire transistor configurations. Anintegrated circuit device according to an embodiment includes asubstrate with a plurality of fins extending from the substrate. Eachfin has a fin height, a fin width, and a fin length, the fin heightincluding an upper channel portion and a lower sub-fin portion. In somesuch embodiments, the fin width is less than 11 nanometers, the finheight is greater than 155 nanometers, and the spacing between any twoneighboring fins of the plurality is less than 30 nanometers. In anotherembodiment, the fin width is less than 15 nanometers, the fin height isgreater than 190 nanometers, and the spacing between any two neighboringfins of the plurality is less than 30 nanometers. Other possible fingeometries will be apparent in light of this disclosure. In any suchcases, each of the fins is in a non-collapsed state. This is because thefins are treated to resist collapse prior to transistor formingprocessing, in accordance with some embodiments. The treatment mayinclude, for example, at least one of a non-polar solvent rinse, asurfactant solution rinse, and a self-assembled monolayer treatmentprior to, during or after wet clean processing. Numerous integratedcircuit configurations employing the treated fins will be apparent.

General Overview

The present disclosure recognizes that under standard manufacturingtechniques, when the fin size and/or fin spacing on a device is reduced,the electrical properties of the fins may be compromised. In particular,when the fins are too narrow in width, when the fins are produced in atight pitch (i.e., small space between adjacent fins), when the fins aretoo tall in fin height, and/or when the fins are too short in finlength, subsequent processing can cause a phenomenon referred to hereinas fin collapse, where adjacent fins collapse onto each other inresponse to cohesive forces and/or adhesion forces. Fin collapse isundesirable and typically renders the device inoperable. Thus, aspectsof the present disclosure are directed to surface modification ortreatment technology to prevent collapse of high aspect rationanostructures such as semiconductor fins used to form FETs. As will beappreciated, the techniques provided herein can be used, for example, tomodify the surface of high aspect ratio fins to reduce the adhesionforces and/or cohesive forces, thereby eliminating or otherwise reducingfin collapse.

FIGS. 1A-1E illustrate integrated circuit structures having various finconfigurations, in accordance with various embodiments of the presentdisclosure. As shown, in each embodiment, the integrated circuitstructure includes a substrate and a plurality of fins extending fromthe substrate. The details on the formation of the fins and thematerials used to construct the integrated circuit devices are discussedin greater detail below, but in general, any desired fin formationprocesses can be used. In one particular embodiment, the fins arepatterned and etched from the substrate, such that the fins are nativeto the substrate. Alternatively, the fins may be formed using an aspectratio trapping (ART) process, where sacrificial fins native to thesubstrate are formed and then removed and replaced with desired finmaterial(s) such as a continuous fin material or a multilayer stack ofdifferent fin materials. The substrate can be, for example, bulk silicon(Si), bulk silicon germanium (SiGe), silicon on insulator (SOI), orgermanium on insulator (GOI), or bulk III-V compound such as galliumarsenide (GaAs), to name a few examples. In a more general sense, thesubstrate can be any suitable platform within which or on whichsemiconductor fins can be formed. The various fin materials andconfigurations will be discussed in turn.

As shown in FIGS. 1A and 1B, each fin has a fin height H, a fin width W,and a fin length L. As shown, the fin length L is longer than the finwidth W. As also illustrated in FIGS. 1A and 1B, each device has a finspacing S which is defined as the distance between facing sidewalls ofneighboring fins. FIG. 1A is an example embodiment of fins that arenative to the substrate such that they are a continuous extension of thesubstrate with no seam. FIG. 1B is an example embodiment of fins whereat least a portion of the fins are native to the substrate in that thelower portion of each fin is a seamless extension of the substrate. Theembodiment illustrated in FIG. 1B also includes an optional oxide layerin the fins that originates from the substrate wafer being SOI. This mayhave desirable electrical characteristics, such as inhibiting sub-finleakage. Other embodiments with replacement fins and planar single andmulti-layers converted to fins are possible as well as will be apparent.Further details on the formation of the fins and the materials used toconstruct the integrated circuit devices are discussed in greater detailbelow.

FIG. 1C illustrates an integrated circuit structure which includesnanowires. One example of such structure is discussed in greater detailin U.S. Pat. No. 9,343,559 titled “Nanowire Transistor Devices andForming Techniques” and assigned to Intel Corporation. FIG. 1Cillustrates a structure where the trench oxide (or other shallow trenchisolation “STI” material) of the structure is recessed, after themultilayer stacks have been provided by an ART-based process. This canbe carried out, for example, by masking the finished multilayer stacks Aand B and etching the STI to a suitable depth, or without a mask byusing a selective etch scheme. Any suitable etch process (e.g., wetand/or dry) can be used. For instance, in one specific exampleembodiment, wherein the STI is implemented with silicon dioxide and eachof the top layers of the multilayers stacks A and B is implemented withsilicon, the STI recess process can be carried out using hydrofluoricacid or other suitable etchant that is selective to the non-STImaterial. As will be appreciated, a mask that is impervious or otherwisesuitably resistant to the STI etchant can be patterned to protect themultilayer stacks A and B, if necessary. The depth of the STI recess canvary from one embodiment to the next, and in this example embodiment isflush with the top of the remaining sacrificial fin material (orpedestal). The depth of the STI recess will depend on factors such asthe number of wires and/or ribbons per transistor (or the height of thechannel portion of the fin, which is generally the portion above theSTI), STI thickness and desired isolation, and/or fin height.

FIG. 1D illustrates an integrated circuit device embodiment whichincludes fins having a non-uniform width. In this particular embodiment,the fins are tapered in that they are narrower at the top than at thebottom. In addition, in this example configuration, there is an STI(shallow trench isolation) layer deposited on top of the substrate. Eachfin includes a lower sub-fin portion and an upper channel portion. Thefin height includes the height of the channel portion and the height ofthe sub-fin portion. The insulation material (such as STI) has a heightto just below the lowermost portion of the channel portion of the finsso as to cover the sub-fin portion but not the channel portion. Asillustrated, in this embodiment, the fin width W is a distance betweenlaterally opposite sidewall surfaces of the fin at the lowermost portionof the channel portion of the fin. In one embodiment, the spacing Sbetween any two neighboring fins is measured between respective sidewallsurfaces of the two neighboring fins at an uppermost portion of thefins. As shown in FIG. 1E discussed below, in another embodiment, thespacing S between any two neighboring fins is measured betweenrespective sidewall surfaces of two neighboring fins at the lowermostportion of the channel portion of the fin.

FIG. 1E illustrates another integrated circuit device embodiment. Thisis a cross section through the active gate and channel region of acompleted transistor. There is an STI (shallow trench isolation) layerdeposited on top of the substrate. Each fin includes a lower sub-finportion and an active fin portion (i.e. upper channel portion). There isa gate insulator on top of the STI layer and around the upper channelportion of the fins. The gate insulator is discussed in more detailbelow. The structure has gate electrode metal deposited over the finsand gate contacts above that (not shown). The fin height H includes theheight of the active fin portion (i.e. channel portion) and the heightof the sub-fin portion. The active portion of the fin is defined as theportion that is wrapped by gate insulator. The insulation material (suchas STI) has a height to just below the lowermost portion of the channelportion of the fins so as to cover the sub-fin portion but not thechannel portion. As illustrated, in this embodiment, the fin width W isa distance between laterally opposite sidewall surfaces of the fin atthe lowermost portion of the channel portion of the fin. As alsoillustrated, in this embodiment, the spacing S between any twoneighboring fins is measured between respective sidewall surfaces of twoneighboring fins at the lowermost portion of the channel portion of thefin.

FIG. 2 illustrates the undesirable occurrence of fin collapse. After thefins are formed, a series of wet processing techniques may occur toprepare the fins for shallow trench isolation (STI). If aqueous basedchemistry is used for the wet processing techniques, the fins may bendover in response to the adhesion forces and/or cohesive forces of theneighboring fins. In particular, as shown in FIG. 2 , adjacent finscollapse towards one another such that two adjacent fins contact eachother. This condition leads to massive device yield loss and isirreversible.

FIG. 3A-3C are illustrations of surface tension, meniscus interaction,and hydrostatic pressure on the fins and FIG. 3D illustrates themathematical equation used to simulate fin deflection based upon surfacetension, meniscus interaction and hydrostatic pressure on the fins. Thecontact angle of 45° is used in these simulations for aqueous wet-cleanchemicals. As shown, fin deflection “x” may be caused by surfacetension, meniscus interaction and hydrostatic pressure. If the findeflection “x” equals ½ of the fin spacing S, then two neighboring finscan be brought into contact with each other, causing fin collapse. Byreducing one or more of the surface tension, meniscus interaction andthe hydrostatic pressure, one can prevent fin collapse. Hydrostaticpressure is neglible for this embodiment so can be neglected.

FIGS. 4A-8C are graphical illustrations depicting the conditions inwhich fin collapse occurs with a fin-based transistor device when thefins are manufactured using standard techniques (i.e. when the fins arenot treated as discussed hereafter.) As will be appreciated in light ofthis disclosure, note that fin collapse may be more likely to occurunder standard manufacturing techniques when the fin width “W” (distancebetween laterally opposite sidewall surfaces of the fin at the lowermostportion of the channel portion of the fin) is less than 15 nanometers,the total fin height “H” is greater than 200 nanometers, and the spacing“S” between any two neighboring fins is less than 30 nanometers asmeasured between respective sidewall surfaces of the two neighboringfins at the lowermost portion of the channel portion (see, for example,FIG. 1E). As will be further appreciated in light of this disclosure,note fin collapse is more prone to occur when the fin length “L” isdecreased, fin width “W” is decreased, and fin spacing “S” is decreaseddue to increasing force levels upon submersion in liquids. A set of fivecase studies are presented below per the methodology outlined in FIGS.3A-3D.

FIG. 4A illustrates when fin collapse will occur under standardmanufacturing techniques when the fin spacing S=30 nanometers and thefin height H=200 nanometers. The dashed line indicates the maximum findeflection that can occur before fin collapse will occur (i.e fins beginto touch) and the solid line represents the fin deflection as a functionof the fin width W. As illustrated, under these specific conditions, thefins will collapse if the fin width W is less than 16 nanometers. Incontrast, in one embodiment of the present disclosure, an integratedcircuit device with a substrate and a plurality of fins is providedwhere the fin width is less than 15 nanometers, the fin height isgreater than 200 nanometers and the spacing between any two neighboringfins is less than 30 nanometers and each of the fins is in anon-collapsed state.

FIG. 4B similarly illustrates when fin collapse will occur understandard manufacturing techniques when the fin width W=11 nanometers andthe fin height H=200 nanometers. The dashed line indicates the maximumfin deflection that can occur before fin collapse will occur and thesolid line represents the fin deflection as a function of the finspacing S. As illustrated, under these specific conditions, the finswill collapse if the fin spacing S is less than 55 nanometers. Incontrast, in one embodiment of the present disclosure, an integratedcircuit device with a substrate and a plurality of fins is providedwhere the fin width is less than 11 nanometers, the fin height isgreater than 200 nanometers and the spacing between any two neighboringfins is less than 53 nanometers and each of the fins is in anon-collapsed state.

FIG. 4C similarly illustrates when fin collapse will occur understandard manufacturing techniques when the fin width W=11 nanometers andthe fin spacing S=30 nanometers. The dashed line indicates the maximumfin deflection that can occur before fin collapse will occur and thesolid line represents the fin deflection as a function of the fin heightH. As illustrated, under these specific conditions, the fins willcollapse if the fin height H is greater than 155 nanometers. As setforth in more detail below, the present disclosure is directed tomethods of treating the fins to prevent fin collapse such that fincollapse does not occur. For example, in one embodiment of the presentdisclosure, an integrated circuit device with a substrate and aplurality of fins is provided where the fin width is less than 11nanometers, the fin height is greater than 155 nanometers and thespacing between any two neighboring fins is less than 30 nanometers andeach of the fins is in a non-collapsed state.

FIG. 5A illustrates when fin collapse will occur under standardmanufacturing techniques when the fin spacing S=30 nanometers and thefin height H=200 nanometers. The dashed line indicates the maximum findeflection that can occur before fin collapse will occur and the solidline represents the fin deflection as a function of the fin width W. Asillustrated, under these specific conditions, the fins will collapse ifthe fin width W is less than 16 nanometers.

FIG. 5B similarly illustrates when fin collapse will occur understandard manufacturing techniques when the fin width W=5 nanometers andthe fin height H=200 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin spacing is less than 240nanometers. In contrast, in one embodiment of the present disclosure, anintegrated circuit device with a substrate and a plurality of fins isprovided where the fin width is less than 5 nanometers, the fin heightis greater than 200 nanometers and the spacing between any twoneighboring fins is less than 240 nanometers and each of the fins is ina non-collapsed state.

FIG. 5C illustrates when fin collapse will occur under standardmanufacturing techniques when the fin width W=5 nanometers and the finspacing S=30 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin height is greater than 80nanometers. As set forth in more detail below, the present disclosure isdirected to methods of treating the fins to prevent fin collapse suchthat fin collapse does not occur. For example, in one embodiment of thepresent disclosure, an integrated circuit device with a substrate and aplurality of fins is provided where the fin width is less than 5nanometers, the fin height is greater than 80 nanometers and the spacingbetween any two neighboring fins is less than 30 nanometers and each ofthe fins is in a non-collapsed state.

FIG. 6A illustrates when fin collapse will occur under standardmanufacturing techniques when the fin spacing S=30 nanometers and thefin height H=200 nanometers, and is identical to FIG. 4A and 5Adiscussed above. As illustrated, under these specific conditions, thefins will collapse if the fin width W is less than 16 nanometers.

FIG. 6B illustrates when fin collapse will occur under standardmanufacturing techniques when the fin width W=15 nanometers and the finheight H=200 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin spacing is less than 30nanometers. In contrast, in one embodiment of the present disclosure, anintegrated circuit device with a substrate and a plurality of fins isprovided where the fin width is less than 15 nanometers, the fin heightis greater than 200 nanometers and the spacing between any twoneighboring fins is less than 30 nanometers and each of the fins is in anon-collapsed state.

FIG. 6C similarly illustrates when fin collapse will occur understandard manufacturing techniques when the fin width W=15 nanometers andthe fin spacing S=30 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin height is greater than 200nanometers. As set forth in more detail below, the present disclosure isdirected to methods of treating the fins to prevent fin collapse suchthat fin collapse does not occur. For example, in one embodiment of thepresent disclosure, an integrated circuit device with a substrate and aplurality of fins is provided where the fin width is less than 15nanometers, the fin height is greater than 200 nanometers and thespacing between any two neighboring fins is less than 30 nanometers andeach of the fins is in a non-collapsed state.

FIG. 7A illustrates when fin collapse will occur under standardmanufacturing techniques when the fin spacing S=50 nanometers and thefin height H=200 nanometers. The dashed line indicates the maximum findeflection that can occur before fin collapse will occur and the solidline represents the fin deflection as a function of the fin width W. Asillustrated, under these specific conditions, the fins will collapse ifthe fin width W is less than 12 nanometers. In contrast, in oneembodiment of the present disclosure, an integrated circuit device witha substrate and a plurality of fins is provided where the fin width isless than 12 nanometers, the fin height is greater than 200 nanometersand the spacing between any two neighboring fins is less than 50nanometers and each of the fins is in a non-collapsed state.

FIG. 7B illustrates when fin collapse will occur under standardmanufacturing techniques when the fin width W=5 nanometers and the finheight H=200 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin spacing S is less than 240nanometers.

FIG. 7C similarly illustrates when fin collapse will occur understandard manufacturing techniques when the fin width W=5 nanometers andthe fin spacing S=50 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin height H is greater than100 nanometers. As set forth in more detail below, the presentdisclosure is directed to methods of treating the fins to prevent fincollapse such that fin collapse does not occur. For example, in oneembodiment of the present disclosure, an integrated circuit device witha substrate and a plurality of fins is provided where the fin width isless than 5 nanometers, the fin height is greater than 100 nanometersand the spacing between any two neighboring fins is less than 50nanometers and each of the fins is in a non-collapsed state.

Finally, FIG. 8A illustrates when fin collapse will occur under standardmanufacturing techniques when the fin spacing S=50 nanometers and thefin height H=200 nanometers. The dashed line indicates the maximum findeflection that can occur before fin collapse will occur and the solidline represents the fin deflection as a function of the fin width W. Asillustrated, under these specific conditions, the fins will collapse ifthe fin width W is less than 12 nanometers.

FIG. 8B similarly illustrates when fin collapse will occur understandard manufacturing techniques when the fin width W=11 nanometers andthe fin height H=200 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin spacing S is less than 55nanometers. In contrast, in one embodiment of the present disclosure, anintegrated circuit device with a substrate and a plurality of fins isprovided where the fin width is less than 11 nanometers, the fin heightis greater than 200 nanometers and the spacing between any twoneighboring fins is less than 53 nanometers and each of the fins is in anon-collapsed state.

FIG. 8C similarly illustrates when fin collapse will occur understandard manufacturing techniques when the fin width W=11 nanometers andthe fin spacing S=50 nanometers. As illustrated, under these specificconditions, the fins will collapse if the fin height H is greater than190 nanometers. As set forth in more detail below, the presentdisclosure is directed to methods of treating the fins to prevent fincollapse such that fin collapse does not occur. For example, in oneembodiment of the present disclosure, an integrated circuit device witha substrate and a plurality of fins is provided where the fin width isless than 11 nanometers, the fin height is greater than 190 nanometersand the spacing between any two neighboring fins is less than 50nanometers and each of the fins is in a non-collapsed state.

As illustrated in FIGS. 1C-1E, and as also set forth in more detailbelow, in one embodiment, there may be one or more layers on top of thesubstrate, such as, but not limited to an STI layer. Each fin includes alower sub-fin portion (which is the portion covered with the STI layer)and an upper channel portion. The channel portion has a height generallyreferred to herein as the active fin height. In this type ofconfiguration, as will be appreciated in light of this disclosure, fincollapse may occur when the fin width “W” is less than 15 nanometers andthe active fin height is greater than 35 nanometers. In one embodiment,the active fin height is between 20 nanometers and 75 nanometers. Inanother embodiment, the active fin height is between 30 nanometers and50 nanometers. In yet another embodiment, the active fin height isbetween 30 nanometers and 40 nanometers. The active fin height is equalto the height of the upper part of the fin having the gate dielectricthereon, and the sub-fin height is equal to the height covered by theinitial STI layers on top of the substrate. As will be appreciated, theinitial STI can be recessed to expose the channel portion of the fins,so that subsequent MOS processing can be carried out (e.g., includingformation of gate, source, and drain regions, and the associated contactstructures). As shown in FIG. 1D and 1E, the total fin height=active finheight+sub-fin height. In one embodiment, the height of the sub-finportion (which is sometimes referred to as a pedestal) is between 150nanometers and 300 nanometers. In another embodiment, the height of thesub-fin portion is between about 150 nanometers and 250 nanometers. Inanother embodiment, the height of the sub-fin portion is between about150 nanometers and 200 nanometers. In yet another embodiment, the heightof the sub-fin portion is between about 200 nanometers and 250nanometers. In yet another embodiment, the height of the sub-fin portionis between about 200 nanometers and 300 nanometers. Numerous suchsub-fin/active fin configurations can be used.

Various fin and substrate materials are discussed in greater detailbelow, but in an embodiment where the fins include a hardmask of eithera single layer or multiple composition layers, such as but not limitedto silicon nitride (SiN), polycrystalline silicon, and silicon dioxide(SiO2), the problems associated with adhesion forces and/or cohesiveforces may be exacerbated, thus leading to fin collapse under standardmanufacturing techniques.

FIG. 9A illustrates a Scanning Electron Microscopy (SEM) image of afin-based integrated circuit structure with some fins shown in acollapsed state. As shown, the collapsed fins may appear as single lineswhere the uppermost portion of neighboring fins are contacting eachother, while the non-collapsed fins may appear as spaced apart doublelines. The SEM image shown in FIG. 9A illustrates a mixture of somecollapsed fins and some non-collapsed fins. FIG. 9A is representative ofa SEM image of a device produced under standard manufacturingtechniques. FIG. 9A illustrates a SEM image of an integrated circuitstructure having a plurality of fins where the fin width is 11nanometers, the fin height is 200 nanometers and the spacing between anytwo neighboring fins is 30 nanometers and each of the fins is in anon-collapsed state. As illustrated in the graphs reproduced in FIGS.4A, 4B, and 4C a device produced under standard manufacturing techniqueswith these dimensions will have some collapsed fins.

FIG. 9B illustrates a SEM image of a fin-based integrated circuitstructure according to one embodiment of the present disclosure wherethere is no fin collapse. As shown, all of the fins are in anon-collapsed state, and thus they all appear as double lines in the SEMimage where a space remains between neighboring fins. As mentionedabove, and as set forth in further detail below, the present disclosurerecognizes that the use of a post-pattern treatment on the fins mayreduce the adhesion forces and/or cohesive forces, and thus eliminate orotherwise reduce the occurrence of fin collapse. FIG. 9B illustrates aSEM image of an integrated circuit structure having a plurality of finswith dimensions identical to the structure depicted in FIG. 9A (i.e. finwith is 11 nanometers, fin height is 200 nanometers and fin spacing is30 nanometers). However, unlike the structure shown in FIG. 9A, thestructure in FIG. 9B was produced with one or more of the post-patterntreatments described in the present disclosure. Accordingly, theadhesion forces and/or cohesive forces are reduced thereby preventingthe occurrence of fin collapse.

Post Fin Formation Treatment

As mentioned above, aspects of the present disclosure are directed tomethods of treating the fins to prevent fin collapse. As will beappreciated in light of this disclosure, a standard post-pattern (i.e.STR etch) rinse containing polar liquids, such as aqueous solutions(like sulfuric acid and/or hydrofluoric acid rinses), may cause orotherwise contribute to fin collapse.

Accordingly, the present disclosure provides alternatives to standardpost-pattern rinse technology. To this end, a plurality of differentpost fin formation treatments is provided herein which may be usedalone, or in combination, to reduce the adhesion and/or cohesive forcesbetween adjacent fins, to thus eliminate fin collapse.

In one embodiment of the present disclosure, a post-pattern treatmentincluding a non-polar solvent is used. In one such embodiment, once thefins are formed (sometimes generally referred to herein as beingpatterned), a treatment with a non-polar solvent may help to reduce theoccurrence of subsequent fin collapse. For example, after the fins areformed on the substrate, the fins may be treated with a non-polarsolvent such as, but not limited to, isopropyl alcohol (IPA), ethanoland/or hexane. In one embodiment, the non-polar solvent may be sprayedonto the fins on the substrate. In another embodiment, the fins on thesubstrate may be cleaned in a wet processing tool plumbed with thenon-polar solvent. In a more general sense, the non-polar solvent may beapplied using any suitable techniques. As will be further appreciated,numerous non-polar solvents may also be used as a post-pattern treatmenton the fins to reduce adhesion and/or cohesive forces and thus reducethe occurrence of fin collapse.

In another embodiment of the present disclosure, a post-patterntreatment including a surfactant may be used to derivatize the surfaceof the fins. A treatment with a surfactant may help to reduce adhesionand/or cohesive forces between the fins and thus reduce the occurrenceof fin collapse. For example, after the fins are formed on thesubstrate, the fins may be treated with a surfactant such as, but notlimited to, soaps, detergents, or ammonia based solutions. In oneembodiment, the surfactant may be sprayed onto the fins on thesubstrate. In another embodiment, the fins on the substrate may besubmerged into a wet bench containing a solution including thesurfactant in an appropriate solvent (aqueous or non-polar as describedabove). In a more general sense, the surfactant may be applied using anysuitable techniques. As will be further appreciated, numerous othersurfactants may also be used as a post-pattern treatment on the fins toreduce the occurrence of fin collapse.

In yet another embodiment of the present disclosure, a post-patterntreatment may include a self-assembled monolayer. For example, after thefins are formed on the substrate, the fins may be treated with aself-assembled monolayer, such as, but not limited to, an amine orfluoride containing self-assembled monolayer, sometimes referred to as aLangmuir-Blodgett monolayer. Such a monolayer may be used to pre-treatthe surface to reduce the cohesive and/or adhesion forces that cause fincollapse. In one embodiment, the self-assembled monolayer may be sprayedonto the fins on the substrate. In another embodiment, the fins on thesubstrate may be processed in a wet bench containing a solutionincluding the self-assembled monolayer. In a more general sense, theself-assembled monolayer may be applied using any suitable techniques.As will be further appreciated, numerous other self-assembled monolayersmay also be used as a post-pattern treatment on the fins to reduce theoccurrence of fin collapse.

Turning to FIG. 10 , a schematic diagram of a self-assembled monolayerwhich may be used in a post-pattern treatment according to oneembodiment of the present disclosure is illustrated. As illustrated, inone embodiment, the self-assembled monolayer includes a head group, atail, and a functional group. The head group may include a compoundconfigured to adhere to the fins when the fins are treated with theself-assembled monolayer, and the functional group may include acompound that is configured not to adhere to the fins, thus reducing theoccurrence of fin collapse.

Table 1, reproduced below, illustrates example compositions for the headgroup, tail, and functional group of the self-assembled monolayer basedupon example fin materials. For example, in one embodiment, when theintegrated circuit device includes fins made of group IV semiconductormaterials such as silicon, silicon germanium (SiGe), or germanium (Ge),the head group of a self-assembled monolayer may be made of silane,ammonia, and/or germane, the tail may be made from butane, propaneand/or carbon, and the functional group may be made of glycerol,hydroxide, and/or fluorine/fluoride. As shown, in another exampleembodiment, when the integrated circuit device includes fins made ofsemiconductor materials classified as group III-V, such as, but notlimited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs),or indium phosphide (LIP), the head group of a self-assembled monolayermay be made from methyl gallium, methyl aluminum, and/or ammonia, thetail may be made from butane, propane and/or carbon, and the functionalgroup may be made of glycerol, hydroxide, and/or fluorine/fluoride. Aswill be appreciated, these are example compositions of theself-assembled monolayer and that, in another embodiment, theself-assembled monolayer may include other compositions as the presentdisclosure is not intended to be limited in this respect.

TABLE 1 Self-Assembled Monolayer Compositions Fin material Head TailFunctional group Silicon or silane butane glycerol SiGe or Ge ammoniapropane hydroxide germane up to 10 carbon fluorine/fluoride chains III-Vi.e. GaAs, methyl butane glycerol InGaAs, InP gallium methyl propanehydroxide aluminum ammonia up to 10 carbon fluorine/fluoride chains

As mentioned above, these post-pattern treatments may be used alone, orin combination, to reduce the adhesion and/or cohesive forces, to thuseliminate fin collapse. In one embodiment all three of theabove-mentioned post-pattern treatments may be used during themanufacturing process to enable one to make smaller-scale integratedcircuit devices with fin patterns that would, without such apost-pattern treatment, have fins in a collapsed state. In otherembodiments, any two of the three treatment types are used on the fins.In one particular embodiment, the fins on the substrate are treatedfirst with a non-polar solvent, second with a surfactant, and third witha self-assembled monolayer. In another embodiment, the post-patterntreatment includes a non-polar solvent and a self-assembled monolayer.In another embodiment, the post-pattern treatment includes a surfactantand a self-assembled monolayer. In yet another embodiment, thepost-pattern treatment includes a non-polar solvent and a surfactant.All possible permutations can be used.

Aspects of the present disclosure are directed to a method for forming afin-based transistor structure. The method includes forming a pluralityof fins on a substrate, each fin extending from the substrate, andtreating the plurality of fins on the substrate with at least one of: aself-assembled monolayer; a non-polar solvent; and a surfactant. Themethod may further include depositing insulation material on opposingsides of each fin and up to a certain height on the fins (or recessingexcess insulation material), so as to leave a top portion of the finsexposed, and forming a gate stack over a channel region of at least oneof the fins, forming source and drain regions adjacent the channelregion, and forming source and drain contacts on the source and drainregions, respectively.

As mentioned above, the treating of the fins on the substrate mayinclude, for example, applying the self-assembled monolayer onto theplurality of fins on the substrate and/or submerging the plurality offins on the substrate in a wet bench containing a solution including theself-assembled monolayer. Treating the plurality of fins on thesubstrate may include treating with the self-assembled monolayer, andthe self-assembled monolayer comprises a head group, a tail, and afunctional group, wherein the head group includes silane, ammonia and/orgermane, the tail group includes butane, propane and/or hydro-carbonchains with 4 to 100 carbon atoms, and the functional group includesglycerol, hydroxide, and/or fluorine/fluoride. In another embodiment,the method includes treating with the self-assembled monolayer, and theself-assembled monolayer comprises a head group, a tail and a functionalgroup, wherein the head group includes methyl gallium, methyl aluminum,and/or ammonia, the tail group includes butane, propane and/or carbon,and the functional group includes glycerol, hydroxide, and/orfluorine/fluoride. In another embodiment, the method includes treatingthe with the self-assembled monolayer, and the self-assembled monolayercomprises a head group, a tail and a functional group, wherein the tailgroup includes butane, propane and/or carbon, and the functional groupincludes glycerol, hydroxide, and/or fluorine/fluoride.

As mentioned above, the treating of the fins on the substrate mayinclude spraying the non-polar solvent onto the plurality of fins on thesubstrate and/or submerging the plurality of fins on the substrate intoa dip tank filled with the non-polar solvent, where the non-polarsolvent is at least one of isopropyl alcohol, ethanol and hexane.

In another embodiment, the method includes the treating of the fins onthe substrate with a surfactant and the surfactant is an ammonia-basedsolution which may include spraying the surfactant onto the plurality offins on the substrate and/or submerging the plurality of fins on thesubstrate into a dip tank filled with the surfactant.

Transistor Device Materials and Construction

The fins may be formed on or from the substrate by a variety ofconventional approaches as the disclosure is not limited in thisrespect. In one embodiment, the substrate may be formed from a bulksilicon substrate and the shallow trench recess (STR) may be etched outof the silicon by standard etch techniques. In one embodiment, theplurality of fins is native to the substrate in that each fin is aseamless extension of the substrate. In another embodiment, theplurality of fins are replacement fins formed on the substrate in thatthere is a seam located at an intermediate height of the fin and thereplacement fins may be formed by standard techniques, such as thosedescribed in U.S. Patent Application Publication 2014/0027860 titled“Self-Aligned 3-D Epitaxial Structures for MOS Device Fabrication” andassigned to Intel Corporation. Such fins can be formed using an aspectratio trapping or so-called ART-based process as previously explainedand will be further discussed in turn.

In one embodiment, there is a first plurality of fins and a secondplurality of fins, each extending from the substrate. Each of the firstand second plurality of fins may be replacement fins in that there is aseam where each of the fins interfaces with the substrate. In anotherembodiment, each of the first and second plurality of fins is native tothe substrate in that each fin is a seamless extension of the substrate.In yet another embodiment, each of the first plurality of fins is nativeto the substrate in that each fin is a seamless extension of thesubstrate, and each of the second plurality of fins is a replacement finin that there is a seam where each such fin interfaces with thesubstrate. In yet another embodiment, at least some of the replacementfins are configured with multilayer stacks of alternating materialsuitable for nanowire configurations.

Any number of suitable substrate configurations can be used here,including bulk substrates, semiconductors on insulator substrates (XOI,where X is a semiconductor material such as Si, Ge or Ge-enriched Si),and multi-layered structures. In one specific example case, thesubstrate is a silicon bulk substrate. In other implementations, thesemiconductor substrate may be formed using alternate materials, whichmay or may not be combined with silicon, that include but are notlimited to germanium, indium antimonide, lead telluride, indiumarsenide, indium phosphide, gallium arsenide, or gallium antimonide.Further semiconductor materials classified as group III-V materials,such as, but not limited to, gallium arsenide (GaAs), indium galliumarsenide (InGaAs), or indium phosphide (InP), may also be used to formthe substrate. Although a few examples of materials from which thesubstrate may be formed are described here, any material that may serveas a foundation upon which a semiconductor device may be built fallswithin the spirit and scope of the disclosure.

The fins can be formed using any number of suitable processes, aspreviously explained. Some embodiments may employ, for example, thedeposition and patterning of a hardmask on the substrate. This can becarried out using standard photolithography, including deposition of ormore hardmask materials (e.g., such as silicon dioxide, silicon nitride,and/or other suitable hardmask materials), patterning resist on aportion of the hardmask that will remain temporarily to protect anunderlying region of the fin (such as a channel or active area of atransistor device), etching to remove the unmasked (no resist) portionsof the hardmask (e.g., using a dry etch, or other suitable hardmaskremoval process), and then stripping the patterned resist material,thereby leaving the patterned mask. In some such embodiments, theresulting hardmask is a two-layer hardmask configured with a bottomlayer of oxide (e.g., native oxide, such as silicon dioxide resultingfrom oxidation of silicon substrate) and top layer of silicon nitride.Any number of suitable mask configurations can be used in forming thefins, as will be apparent.

As can be further seen in FIGS. 11A, 11B, 12A, 12B, and 12C discussedbelow, shallow trenches may be provisioned in the substrate andsubsequently filled with an insulating material so as to provide shallowtrench isolation (STI) about a plurality of fins, in accordance with anembodiment of the present disclosure. Any number of fins can beprovided, and in any number of patterns or configurations suitable for agiven application. The techniques provided herein are particularlywell-suited to tall, narrow and densely spaced fins, as previouslyexplained. The shallow trench etch can be accomplished, for example,with EUV photolithography including wet or dry etching, or a combinationof etches if so desired or by spacer fin patterning using conventional193 nm lithography. The geometry of the trenches (width, depth, shape,etc.) can vary from one embodiment to the next as will be appreciated,and the disclosure is not intended to be limited to any particulartrench geometry. Any number of trench configurations can be useddepending on the desired fin height, as will be apparent. The trenchescan be subsequently filled using any number of suitable depositionprocesses. In one specific example embodiment having a siliconsubstrate, the insulating STI fill material is SiO2, but any number ofsuitable isolation dielectric materials can be used to form the shallowtrench isolation (STI) structures here. In general, the deposited orotherwise grown isolation dielectric material for filling the trenchescan be selected, for example, based on compatibility with the nativeoxide of the substrate material.

While the embodiments shown in FIGS. 1A-1C show fins as having a widththat does not vary with distance from the substrate, as shown in FIG.1D, the fin may be narrower at the top than the bottom in anotherembodiment, or the fins may be wider at the top than the bottom inanother embodiment, or having any other width variations and degrees ofuniformity (or non-uniformity). Further note that the width variationmay, in some embodiments, be symmetrical or asymmetrical. Also, whilethe fins are illustrated as all having the same width, some fins may bewider and/or otherwise shaped differently than other fins on the samesubstrate.

In one embodiment, the fins can be formed using an aspect ratio trapping(ART) methodology, such as that described in the previously noted U.S.Patent Application Publication 2014/0027860. In such cases, the channelmaterial can be provided after so-called placeholder fins are formed andthen recessed or otherwise removed. In more detail, the substrate can bepatterned and etched into placeholder fins formed from the substratematerial. Those fins are then encased in an insulator or other suitablematerial. The place holder fins can then selectively be recessed orotherwise removed and replaced with a desired channel material. In somesuch cases, the replacement channel material can be provided in thecontext of multilayer stacks that include alternating layers of desiredchannel material and sacrificial/inactive material, such as thatdescribed in the previously noted U.S. Pat. No. 9,343,559.

Subsequent processing to form a completed transistor device, which mayinclude for instance, source and drain regions, a final gate stack, andmetal contacts, can be carried out for instance as normally done orusing any custom processing as desired. Numerous configurations will beapparent in light of this disclosure, and the present disclosure is notintended to be limited to any particular one. In addition, some examplesource/drain forming techniques and structures, in accordance withvarious embodiments, are provided in turn with further reference toFIGS. 11A, 11B, 12A, 12B, and 12C, discussed below.

Following formation of the discrete channel regions such as in thevariously example embodiments depicted in FIGS. 1A-1D, gate dielectricand gate electrode processing may be performed, and source and draincontacts may be added, in accordance with some example embodiments. Suchpost-channel processing can be carried out, for instance, as normallydone. Note that gate formation may be carried out using a gate-last orso-called RMG (remove metal gate) process, where dummy gate materialsare first provided over the channel and then later removed and replacedwith the desired gate materials after the source/drain processing iscomplete. Alternatively, the gate formation may be carried out using agate-first process.

In some example embodiments, the gate dielectric can be, for example,any suitable oxide such as SiO₂ or high-k gate dielectric materials.Examples of high-k gate dielectric materials include, for instance,hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanumaluminum oxide, zirconium oxide, zirconium silicon oxide, tantalumoxide, titanium oxide, barium strontium titanium oxide, barium titaniumoxide, strontium titanium oxide, yttrium oxide, aluminum oxide, leadscandium tantalum oxide, and lead zinc niobate. In some embodiments, anannealing process may be carried out on the gate dielectric layer toimprove its quality when a high-k material is used. In general, thethickness of the gate dielectric should be sufficient to electricallyisolate the gate electrode from the source and drain contacts. The gateelectrode material can be, for example, polysilicon, silicon nitride,silicon carbide, or a metal layer (e.g., tungsten, titanium nitride,tantalum, tantalum nitride) although other suitable gate electrodematerials can be used as well. The formed gate electrode may then becovered with a mask to protect it during subsequent processing. The gatedielectric, gate electrode and any optional mask materials can begenerally referred to as a gate stack or gate structure.

Once the gate stack is fabricated (whether the actual gate or a dummygate, depending on the gate forming process used), the source/drainregions can be processed. This processing may include, for example,exposing the source/drain regions by etching or otherwise removing theadditional insulator material from around the fin or replacement fins,so that source drain regions can be doped (ion implantation) oretched-and-replaced with a desired material(s) and structure. Then,source/drain contacts can be provisioned, which may be accomplishedusing a silicide or germanide process, for example. Typical source/drainregion materials include silicon, germanium, SiGe, or III-V materials,and are normally doped either n-type (e.g., phosphorous dopant) orp-type (e.g., boron dopant) to provide NMOS or PMOS transistors,respectively. Typical source drain contact materials include, forexample, tungsten, titanium, silver, gold, aluminum, and alloys thereof.

As will be appreciated, the depicted methodology can be carried outusing any suitable standard semiconductor processes, includinglithography, chemical vapor deposition (CVD), atomic layer deposition(ALD), spin-on deposition (SOD), physical vapor deposition (PVD), wetand dry etching (e.g., isotropic and/or anisotropic), depending on thematerials used and desired profiles. Alternate deposition techniques maybe used as well, for instance, various material layers may be thermallygrown. As will be further appreciated in light of this disclosure, anynumber of suitable materials, layer geometries, and formation processescan be implemented, so as to provide a custom fin-based device orstructure as described herein.

FIGS. 1B and 1C each illustrates an embodiment where the fins includemultiple layers. As can be seen, each fin may include a channel portionthat includes one or more nanowires, each nanowire formed from acorresponding one of the one or more semiconductor layers. As can befurther seen, the multi-layer fins may include one or more insulatorlayers between the one or more semiconductor layers.

FIGS. 11A and 11B each illustrates a perspective view of an integratedcircuit structure that is configured in accordance with one embodimentof the present disclosure. The example non-planar configuration shown inFIG. 11A includes a substrate having a semiconductor body or finextending from the substrate through a shallow trench isolation (STI)layer. The portion of the fin above the STI layer effectively forms thechannel of the transistor device. Recall that the channel portion of thefin may be native to the substrate or an alternative channel material.As can be further seen in FIG. 11A, a gate dielectric material isprovided between the fin and a gate electrode, and a hard mask is formedon top of the gate electrode. Note that the gate electrode is formedover three surfaces of the fin to form three gates (hence, a tri-gatedevice). FIG. 11B illustrates the resulting structure after depositionof insulating material and subsequent etch that leaves a coating of theinsulator material on the vertical surfaces of the gate stack (whichincludes the gate dielectric, gate electrode, and gate hard mask, inthis example case), so as to provide the gate spacers.

The source/drain regions can be formed in the originally provided finstructure in some embodiments. Alternatively, in other embodiments, thesource/drain regions are formed by an etch-and-replace process. Forinstance, FIG. 12A illustrates an example transistor structure aftergrowth of an epitaxial source/drain liner and cap configuration in thesource/drain regions. The epitaxial liner may be, for example, a thinp-type silicon-containing (e.g., silicon or SiGe having 70 atomic %silicon) liner, or a pure germanium (e.g., a separate layer ofgermanium, or a non-detectable layer that is integrated or otherwiseincluded in the composition of the caps). The epitaxial cap can be, forexample, p-type and comprise primarily germanium but may contain lessthan 20 atomic % tin, according to some embodiments. Other embodimentsmay have a single layer source/drain configuration rather than abi-layer structure, or some other desired configuration. Numerous othersource/drain configurations and material system can be used, as will beappreciated.

As will further be appreciated, note that an alternative to the tri-gateconfiguration as shown is a double-gate architecture, which wouldinclude a dielectric/isolation layer on top of the fin, such that thegate resides predominately on the two opposing sides of the fin (again,above the STI region). Further note that the example shapes of theepitaxial liner and cap making up the source/drain regions in thisexample case are not intended to limit the present disclosure to suchshapes; rather, other source/drain shapes will be apparent in light ofthis disclosure (e.g., round, square or rectangular source/drain regionsmay be implemented, whether they be raised, flush, or recessed relativeto the top of the channel layer).

FIG. 12B shows a perspective view of a nanowire transistor structureformed in accordance with one embodiment of the present disclosure. Ananowire transistor (sometimes referred to as gate-all-around FET) isconfigured similarly to a fin-based transistor, but instead of a fin, ananowire is used and the gate material generally surrounds the channelregion on all sides. Depending on the particular design, some nanowiretransistors have, for instance, four effective gates. This exampleembodiment includes two nanowires (generally designated as wire, andintended to include ribbons and nanowires, depending on aspect ratio),although other embodiments can have any number of wires. The nanowirescan be implemented, for example, with p-type silicon or germanium orSiGe or III-V nanowires. As can be seen, one nanowire is formed orotherwise provided on a pedestal of the substrate and the other nanowireeffectively floats in the source/drain material, which in this exampleembodiment is a bi-layer construction comprising liner and cap. Singlelayer constructions may also be used, or any other desired construction.Other embodiments may have a recess in the substrate in which thenanowire is formed (rather than on a pedestal). Just as with the finconfiguration in FIG. 12A, note that the nanowires can be replaced inthe source/drain regions with a single layer or bi-layer or multi-layerconstruction of source/drain material (e.g., relatively thin silicon orgermanium or SiGe liner and relatively thick high concentrationgermanium cap). Alternatively, a multi-layer construction can beprovided around the originally formed nanowire as shown (where the lineris provided around the nanowire, and the cap is then provided around theliner).

FIG. 12C also illustrates another example nanowire configuration havingmultiple nanowires, but in this example case, inactive material (IM) isnot removed from between the individual nanowires during the nanowireforming process, which can be carried out using various standardtechniques. Thus, one nanowire is provided on a pedestal (or recess) ofsubstrate and the other nanowire effectively sits on top of the inactivematerial. Note the nanowires are active through the channel, but theinactive material is not. As can be seen, the bi-layer source/drainconstruction of liner and cap is provided around all other exposedsurfaces of the nanowires. Again, other embodiments may include singlelayer construction or some other multi-layer construction.

Example System

FIG. 13 illustrates a computing system implemented with one or moreintegrated circuit structures configured in accordance with anembodiment of the present disclosure. As can be seen, the computingsystem 1000 houses a motherboard 1002. The motherboard 1002 may includea number of components, including but not limited to a processor 1004and at least one communication chip 1006 (two are shown in thisexample), each of which can be physically and electrically coupled tothe motherboard 1002, or otherwise integrated therein. As will beappreciated, the motherboard 1002 may be, for example, any printedcircuit board, whether a main board or a daughterboard mounted on a mainboard or the only board of system 1000, etc. Depending on itsapplications, computing system 1000 may include one or more othercomponents that may or may not be physically and electrically coupled tothe motherboard 1002. These other components may include, but are notlimited to, volatile memory (e.g., DRAM), non-volatile memory (e.g.,ROM), a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth). Any of the components included in computingsystem 1000 may include one or more integrated circuit structuresconfigured with fin-based transistors having fin dimensions normallysusceptible to fin collapse, as variously explained herein. In someembodiments, multiple functions can be integrated into one or more chips(e.g., for instance, note that the communication chip 1006 can be partof or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for thetransfer of data to and from the computing system 1000. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 1006 may implementany of a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing system 1000 may include a plurality ofcommunication chips 1006. For instance, a first communication chip 1006may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 1006 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integratedcircuit die packaged within the processor 1004. In some embodiments ofthe present disclosure, the integrated circuit die of the processor 1004includes one or more fin-based transistors having high aspect ratio finspre-treated prior to the transistor forming process as variouslyprovided herein. The term “processor” may refer to any device or portionof a device that processes, for instance, electronic data from registersand/or memory to transform that electronic data into other electronicdata that may be stored in registers and/or memory.

The communication chip 1006 may also include an integrated circuit diepackaged within the communication chip 1006. In accordance with somesuch example embodiments, the integrated circuit die of thecommunication chip 1006 includes one or more fin-based transistorshaving high aspect ratio fins pre-treated prior to the transistorforming process as variously provided herein. As will be appreciated inlight of this disclosure, note that multi-standard wireless capabilitymay be integrated directly into the processor 1004 (e.g., wherefunctionality of any chips 1006 is integrated into processor 1004,rather than having separate communication chips). Further note thatprocessor 1004 may be a chip set having such wireless capability. Inshort, any number of processor 1004 and/or communication chips 1006 canbe used. Likewise, any one chip or chip set can have multiple functionsintegrated therein.

In various implementations, the computing system 1000 may be a laptop, anetbook, a notebook, a smartphone, a tablet, a personal digitalassistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer,a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the system 1000may be any other electronic device that processes data or employsfin-based transistor devices as described herein (e.g., CMOS deviceshaving both p and n type devices configured with customized channels onthe same die). As will be appreciated in light of this disclosure,various embodiments of the present disclosure can be used to improveperformance on products fabricated at any process node (e.g., in themicron range, or sub-micron and beyond) by allowing for the use offin-based transistors having high aspect ratio fins pre-treated prior totransistor forming process as variously provided herein.

Further Example Embodiments

The following examples pertain to further embodiments, from whichnumerous permutations and configurations will be apparent.

Example 1 is an integrated circuit device, including a substrate, and afirst plurality of fins extending from the substrate, each fin having afin height, a fin width, and a fin length, the fin height including anupper channel portion and a lower sub-fin portion, the fin width being adistance between laterally opposite sidewall surfaces of the fin at thelowermost portion of the channel portion of the fin, and the fin lengthbeing longer than the fin width, wherein the fin width is less than 11nanometers, the fin height is greater than 155 nanometers, and whereinspacing between any two neighboring fins of the plurality is less than30 nanometers as measured between respective sidewall surfaces of thetwo neighboring fins at the lowermost portion of the channel portion,and each of the first plurality of fins is in a non-collapsed state.

Example 2 is the device of Example 1, wherein each of the firstplurality of fins is a replacement fin in that there is a seam along theheight of the fin.

Example 3 is the device of Example 1, wherein each of the firstplurality of fins is native to the substrate in that each such fin is aseamless extension of the substrate.

Example 4 is the device of any of the preceding Examples 1-3, furtherincluding a second plurality of other fins extending from the substrate.

Example 5 is the device of Example 4, wherein each of the secondplurality of fins has a fin height, a fin width, and a fin length, thefin height including an upper channel fin portion and a lower sub-finportion, the fin width being a distance between laterally oppositesidewall surfaces of the fin at the lowermost portion of the channelportion of the fin, and the fin length being longer than the fin width,wherein the fin width is less than 11 nanometers, the fin height isgreater than 155 nanometers, and wherein spacing between any twoneighboring fins of the plurality is less than 30 nanometers as measuredbetween respective sidewall surfaces of the two neighboring fins at thelowermost portion of the channel portion, and each of the secondplurality of fins is in a non-collapsed state.

Example 6 is the device of Example 4, wherein each of the firstplurality of fins include a first semiconductor composition, and each ofthe second plurality of fins include a second semiconductor compositiondifferent from the first semiconductor composition.

Example 7 is the device of any of the preceding Examples, wherein atleast some of the first plurality of fins has a fin length less than 200nanometers.

Example 8 is the device of any of the preceding Examples, wherein thechannel portion has a height that is greater than 35 nanometers.

Example 9 is the device of any of the preceding Examples, furtherincluding a shallow trench isolation on the substrate and opposing sidesof the sub-fin portion of each of the first plurality of fins, a gatestack over each channel portion, the gate stack including a gatedielectric and a gate electrode, and source and drain regionscorresponding to each channel portion.

Example 10 is the device of any of Examples 1-8, further including ashallow trench isolation (STI) material on the substrate and betweenfins of the first plurality, the STI material having a height to justbelow the lowermost portion of the channel portion of the fins so as tocover the sub-fin portion but not the channel portion, a gate electrodeover the channel portion of each of the fins, a gate dielectricpositioned between the gate electrode and the channel portion of each ofthe fins, and a source region and a drain region each at least one of onand in each of the first plurality of fins and adjacent thecorresponding channel portion, such that the corresponding channelportion is between the source and drain regions.

Example 11 is the device of any of the preceding Examples, wherein thesubstrate is a multi-layer substrate having one or more semiconductorlayers, and the first plurality of fins are formed from at least one ofthe one or more semiconductor layers.

Example 12 is the device of Example 11, wherein the multi-layersubstrate includes one or more insulator layers between the one or moresemiconductor layers.

Example 13 is the device of any of the preceding Examples, wherein eachfin includes a channel portion that includes one or more nanowires, eachnanowire formed from a corresponding one of the one or moresemiconductor layers.

Example 14 is the device of any of the preceding Examples, furtherincluding a gate stack over each channel portion, the gate stackincluding a gate dielectric and a gate electrode, and source and drainregions corresponding to each channel portion.

Example 15 is a system-on-chip including the device of any of any of thepreceding Examples.

Example 16 is a computing system including the integrated circuitstructure of any of any of the Examples 1-14.

Example 17 is an integrated circuit device, including a substrate, and afirst plurality of fins extending from the substrate, each fin having afin height, a fin width, and a fin length, the fin height including anupper channel portion and a lower sub-fin portion, the fin width being adistance between laterally opposite sidewall surfaces of the fin at thelowermost portion of the channel portion of the fin, and the fin lengthbeing longer than the fin width, wherein the fin width is less than 15nanometers, the fin height is greater than 190 nanometers, and whereinspacing between any two neighboring fins of the plurality is less than30 nanometers as measured between respective sidewall surfaces of thetwo neighboring fins at the lowermost portion of the channel portion,and each of the first plurality of fins is in a non-collapsed state.

Example 18 is the device of Example 17, wherein each of the firstplurality of fins is a replacement fin in that there is a seam along theheight of the fin.

Example 19 is the device of Example 17, wherein each of the firstplurality of fins is native to the substrate in that each such fin is aseamless extension of the substrate.

Example 20 is the device of any of Examples 17-19, further including asecond plurality of other fins extending from the substrate.

Example 21 is the device of Example 20, wherein each of the secondplurality of fins has a fin height, a fin width, and a fin length, thefin height including an upper channel fin portion and a lower sub-finportion, the fin width being a distance between laterally oppositesidewall surfaces of the fin at the lowermost portion of the channelportion of the fin, and the fin length being longer than the fin width,wherein the fin width is less than 15 nanometers, the fin height isgreater than 190 nanometers, and wherein spacing between any twoneighboring fins of the plurality is less than 30 nanometers as measuredbetween respective sidewall surfaces of the two neighboring fins at thelowermost portion of the channel portion, and each of the secondplurality of fins is in a non-collapsed state.

Example 22 is the device of any of Examples 20-21, wherein each of thefirst plurality of fins include a first semiconductor composition, andeach of the second plurality of fins include a second semiconductorcomposition different from the first semiconductor composition.

Example 23 is the device of any of Examples 17-22, wherein at least someof the first plurality of fins has a fin length less than 200nanometers.

Example 24 is the device of any of Examples 17-23, wherein the channelportion has a height that is greater than 35 nanometers.

Example 25 is the device of any of Examples 17-24, further including ashallow trench isolation on the substrate and opposing sides of thesub-fin portion of each of the first plurality of fins, a gate stackover each channel portion, the gate stack including a gate dielectricand a gate electrode, and source and drain regions corresponding to eachchannel portion.

Example 26 is the device of any of Examples 17-24, further including ashallow trench isolation (STI) material on the substrate and betweenfins of the first plurality, the STI material having a height to justbelow the lowermost portion of the channel portion of the fins so as tocover the sub-fin portion but not the channel portion, a gate electrodeover the channel portion of each of the fins, a gate dielectricpositioned between the gate electrode and the channel portion of each ofthe fins, and a source region and a drain region each at least one of onand in each of the first plurality of fins and adjacent thecorresponding channel portion, such that the corresponding channelportion is between the source and drain regions.

Example 27 is the device of any of Examples 17-26, wherein the substrateis a multi-layer substrate having one or more semiconductor layers, andthe first plurality of fins are formed from at least one of the one ormore semiconductor layers.

Example 28 is the device of Example 27, wherein the multi-layersubstrate includes one or more insulator layers between the one or moresemiconductor layers.

Example 29 is the device of any of Examples 17-28, wherein each finincludes a channel portion that includes one or more nanowires, eachnanowire formed from a corresponding one of the one or moresemiconductor layers.

Example 30 is the device of any of Examples 17-29, further including agate stack over each channel portion, the gate stack including a gatedielectric and a gate electrode, and source and drain regionscorresponding to each channel portion.

Example 31 is a system-on-chip including the device of any of Examples17 through 30.

Example 32 is a computing system including the integrated circuitstructure of any of Examples 17 through 30.

Example 33 is an integrated circuit device, including a substrate, and afirst plurality of fins extending from the substrate, each fin having afin height, a fin width, and a fin length, the fin height including anupper channel portion and a lower sub-fm portion, the fin width being adistance between laterally opposite sidewall surfaces of the fin at thelowermost portion of the channel portion of the fin, and the fin lengthbeing longer than the fin width, wherein the fin width is less than 5nanometers, the fin height is greater than 80 nanometers, and whereinspacing between any two neighboring fins of the plurality is less than30 nanometers as measured between respective sidewall surfaces of thetwo neighboring fins at the lowermost portion of the channel portion,and each of the first plurality of fins is in a non-collapsed state.

Example 34 is the device of Example 33, further including a secondplurality of other fins extending from the substrate.

Example 35 is the device of Example 34, wherein each of the secondplurality of fins has a fin height, a fin width, and a fin length, thefin height including an upper channel fin portion and a lower sub-finportion, the fin width being a distance between laterally oppositesidewall surfaces of the fin at the lowermost portion of the channelportion of the fin, and the fin length being longer than the fin width,wherein the fin width is less than 5 nanometers, the fin height isgreater than 80 nanometers, and wherein spacing between any twoneighboring fins of the plurality is less than 30 nanometers as measuredbetween respective sidewall surfaces of the two neighboring fins at thelowermost portion of the channel portion, and each of the secondplurality of fins is in a non-collapsed state.

Example 36 is the device of any of Examples 33-35, wherein at least someof the first plurality of fins has a fin length less than 200nanometers.

Example 37 is the device of any of Examples 33-36, wherein the channelportion has a height that is greater than 35 nanometers.

Example 38 is the device of any of Examples 33-37, further including ashallow trench isolation on the substrate and opposing sides of thesub-fin portion of each of the first plurality of fins, a gate stackover each channel portion, the gate stack including a gate dielectricand a gate electrode, and source and drain regions corresponding to eachchannel portion.

Example 39 is an integrated circuit device, including a substrate, and afirst plurality of fins extending from the substrate, each fin having afin height, a fin width, and a fin length, the fin height including anupper channel portion and a lower sub-fin portion, the fin width being adistance between laterally opposite sidewall surfaces of the fin at thelowermost portion of the channel portion of the fin, and the fin lengthbeing longer than the fin width, wherein the fin width is less than 5nanometers, the fin height is greater than 100 nanometers, and whereinspacing between any two neighboring fins of the plurality is less than50 nanometers as measured between respective sidewall surfaces of thetwo neighboring fins at the lowermost portion of the channel portion,and each of the first plurality of fins is in a non-collapsed state.

Example 40 is the device of Example 39, further including a secondplurality of other fins extending from the substrate.

Example 41 is the device of Example 39, wherein each of the secondplurality of fins has a fin height, a fin width, and a fin length, thefin height including an upper channel fin portion and a lower sub-finportion, the fin width being a distance between laterally oppositesidewall surfaces of the fin at the lowermost portion of the channelportion of the fin, and the fin length being longer than the fin width,wherein the fin width is less than 5 nanometers, the fin height isgreater than 100 nanometers, and wherein spacing between any twoneighboring fins of the plurality is less than 50 nanometers as measuredbetween respective sidewall surfaces of the two neighboring fins at thelowermost portion of the channel portion, and each of the secondplurality of fins is in a non-collapsed state.

Example 42 is the device of any of Examples 39-41, wherein at least someof the first plurality of fins has a fin length less than 200nanometers.

Example 43 is the device of any of Examples 39-42, wherein the channelportion has a height that is greater than 35 nanometers.

Example 44 is the device of any of Examples 39-43, further including ashallow trench isolation on the substrate and opposing sides of thesub-fin portion of each of the first plurality of fins, a gate stackover each channel portion, the gate stack including a gate dielectricand a gate electrode, and source and drain regions corresponding to eachchannel portion.

Example 45 is an integrated circuit device, including a substrate, and afirst plurality of fins extending from the substrate, each fin having afin height, a fin width, and a fin length, the fin height including anupper channel portion and a lower sub-fin portion, the fin width being adistance between laterally opposite sidewall surfaces of the fin at thelowermost portion of the channel portion of the fin, and the fin lengthbeing longer than the fin width, wherein the fin width is less than 11nanometers, the fin height is greater than 190 nanometers, and whereinspacing between any two neighboring fins of the plurality is less than50 nanometers as measured between respective sidewall surfaces of thetwo neighboring fins at the lowermost portion of the channel portion,and each of the first plurality of fins is in a non-collapsed state.

Example 46 is the device of Example 45, further including a secondplurality of other fins extending from the substrate.

Example 47 is the device of Example 45, wherein each of the secondplurality of fins has a fin height, a fin width, and a fin length, thefin height including an upper channel fin portion and a lower sub-finportion, the fin width being a distance between laterally oppositesidewall surfaces of the fin at the lowermost portion of the channelportion of the fin, and the fin length being longer than the fin width,wherein the fin width is less than 11 nanometers, the fin height isgreater than 190 nanometers, and wherein spacing between any twoneighboring fins of the plurality is less than 50 nanometers as measuredbetween respective sidewall surfaces of the two neighboring fins at thelowermost portion of the channel portion, and each of the secondplurality of fins is in a non-collapsed state.

Example 48 is the device of any of Examples 45-47, wherein at least someof the first plurality of fins has a fin length less than 200nanometers.

Example 49 is the device of any of Examples 45-48, wherein the channelportion has a height that is greater than 35 nanometers.

Example 50 is the device of any of Examples 45-49, further including ashallow trench isolation on the substrate and opposing sides of thesub-fin portion of each of the first plurality of fins, a gate stackover each channel portion, the gate stack including a gate dielectricand a gate electrode, and source and drain regions corresponding to eachchannel portion.

Example 51 is a method for forming a fin-based transistor structure, themethod including forming a plurality of fins on a substrate, each finextending from the substrate, and treating the plurality of fins on thesubstrate with at least one of: a self-assembled monolayer; a non-polarsolvent; and a surfactant.

Example 52 is the method of Example 51, further including providinginsulation material on opposing sides of each fin, so as to leave a topportion of the fins exposed, and forming a gate stack over a channelregion of at least one of the fins, forming source and drain regionsadjacent the channel region, and forming source and drain contacts onthe source and drain regions, respectively.

Example 53 is the method of any of Examples 51-52, wherein treating theplurality of fins on the substrate includes spraying the self-assembledmonolayer onto the plurality of fins on the substrate.

Example 54 is the method of any of Examples 51-53, wherein treating theplurality of fins on the substrate includes submerging the plurality offins on the substrate into a solution including the self-assembledmonolayer.

Example 55 is the method of any of Examples 51-54, wherein treating theplurality of fins on the substrate includes treating with theself-assembled monolayer, and the self-assembled monolayer includes ahead group, a tail, and a functional group, wherein the head groupincludes silane, ammonia and/or germane, the tail group includes butane,propane and/or carbon, and the functional group includes glycerol,hydroxide, and/or fluorine/fluoride.

Example 56 is the method of any of Examples 51-54, wherein treating theplurality of fins on the substrate includes treating with theself-assembled monolayer, and the self-assembled monolayer includes ahead group, a tail, and a functional group, wherein the head groupincludes methyl gallium, methyl aluminum, and/or ammonia, the tail groupincludes butane, propane and/or carbon, and the functional groupincludes glycerol, hydroxide, and/or fluorine/fluoride.

Example 57 is the method of any of Examples 51-54, wherein treating theplurality of fins on the substrate includes treating with theself-assembled monolayer, and the self-assembled monolayer includes ahead group, a tail, and a functional group, wherein the tail groupincludes butane, propane and/or carbon, and the functional groupincludes glycerol, hydroxide, and/or fluorine/fluoride.

Example 58 is the method of any of Examples 51-57, wherein treating theplurality of fins on the substrate includes treating with the non-polarsolvent, and the non-polar solvent is at least one of isopropyl alcohol,ethanol and hexane.

Example 59 is the method of any of Examples 51-58, wherein treating theplurality of fins on the substrate includes spraying the non-polarsolvent onto the plurality of fins on the substrate.

Example 60 is the method of any of Examples 51-59, wherein treating theplurality of fins on the substrate includes submerging the plurality offins on the substrate into a solution including the non-polar solvent.

Example 61 is the method of any of Examples 51-60, wherein treating theplurality of fins on the substrate includes treating with thesurfactant, and the surfactant is an ammonia based solution.

Example 62 is the method of any of Examples 51-61, wherein treating theplurality of fins on the substrate includes spraying the surfactant ontothe plurality of fins on the substrate.

Example 63 is the method of any of Examples 51-62, wherein treating theplurality of fins on the substrate includes submerging the plurality offins on the substrate into a solution including the surfactant.

Example 64 is the method of any of Examples 51-63, wherein treating theplurality of fins on the substrate includes treating with at least twoof the surfactant, the non-polar solvent, and the self-assembledmonolayer.

Example 65 is the method of any of Examples 51-64, wherein treating theplurality of fins on the substrate includes treating with each of thesurfactant, the non-polar solvent, and the self-assembled monolayer.

Example 66 is an integrated circuit device, including a plurality offins extending from a substrate, each fin having a fin height, a finwidth, and a fin length, wherein each fin further includes a channelportion and a sub-fin portion, wherein the fin height includes theheight of the channel portion and the height of the sub-fin portion, thefin width being a distance between laterally opposite sidewall surfacesof the fin at the lowermost portion of the channel portion of the fin,and the fin length is longer than the fin width, wherein the fin widthis less than 11 nanometers, the fin height is greater than 155nanometers, wherein spacing between any two neighboring fins of theplurality is less than 30 nanometers as measured between respectivesidewall surfaces of the two neighboring fins at the lowermost portionof the channel portion, and wherein each of the plurality of fins is ina non-collapsed state, a gate dielectric on the channel portion of eachof the fins, including a top of each fin and the laterally oppositesidewalls not covered by insulation material, and a source region and adrain region each adjacent the corresponding channel portion, such thatthe corresponding channel portion is between the source and drainregions.

Example 67 is the device of Example 66, wherein at least some of thefins have a fin length less than 200 nanometers.

Example 68 is the device of any of Examples 66-67, wherein the channelportion of at least some of the fins includes nanowires.

Example 69 is a system-on-chip including the device of any of Examples66-68.

Example 70 is a computing system including the integrated circuit of anyof Examples 66-68.

The foregoing description of example embodiments of the disclosure hasbeen presented for the purposes of illustration and description. It isnot intended to be exhaustive or to limit the disclosure to the preciseforms disclosed. Many modifications and variations are possible in lightof this disclosure. For instance, while the techniques are discussedprimarily in the context of forming transistors such as FETs, otherdevices can be made as well such as diodes, variable capacitors, dynamicresistors, etc. It is intended that the scope of the disclosure belimited not by this detailed description, but rather by the claimsappended hereto.

1. An integrated circuit device, comprising: a substrate; a first fin and a second fin extending from the substrate, wherein each of the first and second fins includes a lower portion and an upper portion; and isolation material adjacent at least the lower portions of the first and second fins; wherein each of the first and second fins is in a non-collapsed state, wherein a horizontal width of each of the first and second fins is a distance between sidewall surfaces of the fin at the bottom of the upper portion of the fin, the horizontal width of the first and second fins is less than 11 nm, wherein a vertical total height, for each of the first and second fins, is a sum of a first height of the lower portion of the fin and a second height of the upper portion of the fin, the vertical total height each of the first and second fins is greater than 200 nm, and wherein a horizontal spacing between the first and second fins is less than 53 nm as measured between respective sidewall surfaces of the first and second fins at the respective bottoms of the upper portions of the first and second fins. 2.-20. (canceled) 